Knapsack problems: algorithms and computer implementations
Knapsack problems: algorithms and computer implementations
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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EDTC '96 Proceedings of the 1996 European conference on Design and Test
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ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
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Interprocedural path profiling and the interprocedural express-lane transformation
Algorithmic aspects of hardware/software partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Area efficiency is one of the major considerations in constraint aware hardware/software partitioning process. This paper focuses on the algorithmic aspects for hardware/software partitioning with the objective of minimizing area utilization under the constraints of execution time and power consumption. An efficient heuristic algorithm running in O(n log n) is proposed by extending the method devised for solving the 0-1 knapsack problem. Also, an exact algorithm based on dynamic programming is proposed to produce the optimal solution for small-sized problems. Simulation results show that the proposed heuristic algorithm yields very good approximate solutions while dramatically reducing the execution time.