Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Sams Teach Yourself ASP.NET in 21 Days
Sams Teach Yourself ASP.NET in 21 Days
WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture
ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
Web-based training on computer architecture: the case for JCachesim
WCAE '02 Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture
MipsIt: a simulation and development environment using animation for computer architecture education
WCAE '02 Proceedings of the 2002 workshop on Computer architecture education: Held in conjunction with the 29th International Symposium on Computer Architecture
MARS: an education-oriented MIPS assembly language simulator
Proceedings of the 37th SIGCSE technical symposium on Computer science education
MIPSPILOT: a compiler-oriented MIPS simulator
Journal of Computing Sciences in Colleges
A complete design of a RISC processor for pedagogical purposes
Journal of Computing Sciences in Colleges
A full system x86 simulator for teaching computer organization
Proceedings of the 42nd ACM technical symposium on Computer science education
Emumaker86: a hardware simulator for teaching CPU design
Proceeding of the 44th ACM technical symposium on Computer science education
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We have implemented a MIPS simulation environment called WebMIPS. Our simulator is accessible from the Web and has been successfully used in introductory computer architecture course at Faculty of Information Engineering in Siena, Italy. The advantages of the Web approach are immediate access to the simulator, without installation, and a possible centralized monitoring of students' activity. WebMIPS is capable of uploading and assembling the MIPS code provided by user, simulating a five-stage pipeline step by step or completely, and displaying the values of all registers, input and output data of all pipeline elements.