Parallel DEVS: a parallel, hierarchical, modular modeling formalism and its distributed simulator
Transactions of the Society for Computer Simulation International
Technical note: a hierarchical computer architecture design and simulation environment
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on Web-based modeling and simulation
DEVS and HLA: complementary paradigms for modeling and simulation?
Transactions of the Society for Computer Simulation International - Ethical issues in modeling and simulation
Theory of Modeling and Simulation
Theory of Modeling and Simulation
CD++: a toolkit to develop DEVS models
Software—Practice & Experience
MiniMIPS: a simulation project for the computer architecture laboratory
SIGCSE '03 Proceedings of the 34th SIGCSE technical symposium on Computer science education
Experiences in modeling and simulation of computer architectures in DEVS
Transactions of the Society for Computer Simulation International - Recent advances in DEVS methodology--part II
Journal of Intelligent and Robotic Systems
Computer Organization and Design
Computer Organization and Design
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
MARS: an education-oriented MIPS assembly language simulator
Proceedings of the 37th SIGCSE technical symposium on Computer science education
Continuous System Simulation
WebMIPS: a new web-based MIPS simulation environment for computer architecture education
WCAE '04 Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture
NoC simulation modeling in DEVS-suite
Proceedings of the 2011 Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium
Standardizing DEVS models: an endogenous standpoint
Proceedings of the 2011 Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium
Real-time network-on-chip simulation modeling
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
DS-RT '13 Proceedings of the 2013 IEEE/ACM 17th International Symposium on Distributed Simulation and Real Time Applications
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Processor concepts, implementation details, and performance analysis are fundamental in computer architecture education, and MIPS (microprocessor without interlocked pipeline stages) processor designs are used by many universities in teaching the subject. In this paper we present a MIPS32 processor simulator, which enriches studentsâ聙聶 learning and instructorsâ聙聶 teaching experiences. A family of single-cycle, multi-cycle, and pipeline processor models for the MIPS32 architecture are developed according to the parallel Discrete Event System Specification (DEVS) modeling formalism. A collection of elementary sequential and combinational model components along with the processor models are implemented in DEVS-Suite. The simulator supports multi-level model abstractions, register-transfer level animation, performance data collection, and time-based trajectory observation. These features, which are partially supported by a few existing simulators, enable important structural and behavioral details of computer architectures to be described and understood. The MIPS processor models can be reused and systematically extended for modeling and simulating other MIPS processors.