Design of a hardware accelerator for path planning on the Euclidean distance transform

Authors:
N. Sudha;A. R. Mohan
Affiliations:
Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore;Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2008

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Abstract

This paper presents a novel hardware-directed algorithm for finding a path for a mobile robot using the Euclidean distance transform of the binary image of an environment. The robot can translate as well as rotate. The path obtained from start to goal is the shortest in terms of the number of steps. The mapping of the algorithm to hardware is described. Results of efficient implementation on a Xilinx FPGA device show that the device can be operated at a clock rate of about 65MHz. Such a high frequency of operation leads to computing a collision-free path on sample images of size 128x128 in less than 3ms and hence the hardware can process images at a video rate. This is necessary for real-time path planning in a dynamic environment.