Automated extraction of expert knowledge in analog topology selection and sizing

Authors:
Trent McConaghy;Pieter Palmers;Georges Gielen;Michiel Steyaert
Affiliations:
K. U. Leuven, Leuven, Belgium and Solido Design Automation Inc., Saskatoon, Canada;ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium;ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium;ESAT-MICAS, K. U. Leuven, Kasteelpark Arenberg, Leuven, Belgium
Venue:
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Year:
2008

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Abstract

This paper presents a methodology for analog designers to maintain their insights into the relationship among performance specifications, topology choice, and sizing variables, despite those insights being constantly challenged by changing process nodes and new specs. The methodology is to take a data-mining perspective on a Pareto Optimal Set of sized analog circuit topologies, then doing: extraction of a specs-to-topology decision tree; global nonlinear sensitivity analysis on topology and sizing variables; and determining analytical expressions of performance tradeoffs. These approaches are all complementary as they answer different designer questions. Once the knowledge is extracted, it can be readily distributed to help other designers, without needing further synthesis. Results are shown for operational amplifier design on a database containing thousands of Pareto Optimal designs across five objectives.