Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Non-uniform micro-channel design for stacked 3D-ICs
Proceedings of the 48th Design Automation Conference
3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling
Proceedings of the International Conference on Computer-Aided Design
Fast thermal analysis on GPU for 3D-ICs with integrated microchannel cooling
Proceedings of the International Conference on Computer-Aided Design
Accelerating thermal simulations of 3D ICs with liquid cooling using neural networks
Proceedings of the great lakes symposium on VLSI
Fast poisson solvers for thermal analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
3D transient thermal solver using non-conformal domain decomposition approach
Proceedings of the International Conference on Computer-Aided Design
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Integrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware thermal model for integrated microchannel 3D ICs. Validation results show the proposed thermal model achieves more than 400x speed up and only 2.0% error in comparison with a commercial numerical simulation tool. We also demonstrate the use of the proposed thermal model for thermal optimization during the IC placement stage. We find that due to the thermal-wake effect, tiles are placed in the descending order of power magnitude along the flow direction. We also find that modeling thermal-wakes is critical for generating a thermal-aware placement for integrated microchannel-cooled 3D IC. It could result in up to 25°C peak temperature difference according to our experiments.