Compaan: deriving process networks from Matlab for embedded signal processing architectures
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Translating Imperative Affine Nested Loop Programs into Process Networks
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Algorithmic transformation techniques for efficient exploration of alternative application instances
Proceedings of the tenth international symposium on Hardware/software codesign
Deriving process networks from weakly dynamic applications in system-level design
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Translating affine nested-loop programs to process networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
pn: a tool for improved derivation of process networks
EURASIP Journal on Embedded Systems
An Input Triggered Polymorphic ASIC for H.264 Decoding
ASAP '09 Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A comparison between an automated, and a semicustom design, and synthesis of a H.264 restricred baseline profile decoder is the subject of this paper. The automated approach models the H.264 decoder as a Kahn Process Network (KPN), that is mapped on a multi-processor Field Programmable Gate Array (FPGA) execution platform. The semi-custom approach follows a BlueSpec design path, including Verilog code generation, compilation, and simulation, and the Xilinx Integrated Software Environment (ISE) tool chain for Xilinx Vertex-II FPGA synthesis. There is still a gap between automated and partially handcrafted design times, even when performance and cost parameters are otherwise comparable, and even when obvious limitations are avoided in both approaches. The purpose of the case study presented here is to pinpoint limitations and challenges when trying to close the gap.