Limits for automatic verification of finite-state concurrent systems
Information Processing Letters
Completing the temporal picture
Selected papers of the 16th international colloquium on Automata, languages, and programming
Forward and backward simulations I.: untimed systems
Information and Computation
Abstract interpretation of reactive systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Model checking
Some Deadlock Properties of Computer Systems
ACM Computing Surveys (CSUR)
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Abstracting WS1S Systems to Verify Parameterized Networks
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Parameterized Verification of a Cache Coherence Protocol: Safety and Liveness
VMCAI '02 Revised Papers from the Third International Workshop on Verification, Model Checking, and Abstract Interpretation
Circular Compositional Reasoning about Liveness
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of Infinite State Systems by Compositional Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Liveness with (0, 1, infty)-Counter Abstraction
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Abstractions for Preserving All CTL* Formulae
Abstractions for Preserving All CTL* Formulae
Liveness with invisible ranking
International Journal on Software Tools for Technology Transfer (STTT)
Proceedings of the 2007 ACM symposium on Applied computing
Computing Invariants for Parameter Abstraction
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Going with the flow: parameterized verification using message flows
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Automatic non-interference lemmas for parameterized model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Industrial Strength Distributed Explicit State Model Checking
PDMC-HIBI '10 Proceedings of the 2010 Ninth International Workshop on Parallel and Distributed Methods in Verification, and Second International Workshop on High Performance Computational Systems Biology
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An important problem in the verification of hardware protocols is that of proving deadlock freedom. We view deadlock freedom as the property that for all reachable states, there exists some path to a quiescent state, i.e. one wherein all resources of interest are free and thus all prior requests have been resolved. We establish a framework for showing this property in a class of symmetric parameterized systems. Our approach is based on a mixed abstraction system than includes both an over-approximate and an under-approximate transition relation. Model checking is employed to compute all states reachable through overapproximate transitions, and from each of these states finds a path of underapproximate transitions to a quiescent state. When this fails because the under-approximation is too strong, we provide techniques to suggest additional transitions that can be introduced to soundly weaken the under-approximation. This approach can be viewed as an extension of the well-known approach of guard strengthening for verifying state invariants of parameterized systems. We present proof of deadlock freedom of the German and FLASH cache-coherence protocols as case studies using a semi-automated heuristic tool that mitigates the human effort.