The diameter of a cycle plus a random matching
SIAM Journal on Discrete Mathematics
The de Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI
IEEE Transactions on Computers
A Variation on the Hypercube with Lower Diameter
IEEE Transactions on Computers
Distributed loop computer networks: a survey
Journal of Parallel and Distributed Computing
High-Performance Routing in Networks of Workstations with Irregular Topology
IEEE Transactions on Parallel and Distributed Systems
Properties and Performance of Folded Hypercubes
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Deadlock-Free Dynamic Reconfiguration Schemes for Increased Network Dependability
IEEE Transactions on Parallel and Distributed Systems
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
On the Feasibility of Optical Circuit Switching for High Performance Computing Systems
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
The BlackWidow High-Radix Clos Network
Proceedings of the 33rd annual international symposium on Computer Architecture
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
IEEE Transactions on Parallel and Distributed Systems
Technology-Driven, Highly-Scalable Dragonfly Topology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Packaging the Blue Gene/L supercomputer
IBM Journal of Research and Development
Small-world networks: from theoretical bounds to practical systems
OPODIS'07 Proceedings of the 11th international conference on Principles of distributed systems
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms
IEEE Transactions on Parallel and Distributed Systems
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip
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As the scales of parallel applications and platforms increase the negative impact of communication latencies on performance becomes large. Fortunately, modern High Performance Computing (HPC) systems can exploit low-latency topologies of high-radix switches. In this context, we propose the use of random shortcut topologies, which are generated by augmenting classical topologies with random links. Using graph analysis we find that these topologies, when compared to non-random topologies of the same degree, lead to drastically reduced diameter and average shortest path length. The best results are obtained when adding random links to a ring topology, meaning that good random shortcut topologies can easily be generated for arbitrary numbers of switches. Using flit-level discrete event simulation we find that random shortcut topologies achieve throughput comparable to and latency lower than that of existing non-random topologies such as hypercubes and tori. Finally, we discuss and quantify practical challenges for random shortcut topologies, including routing scalability and larger physical cable lengths.