Reconfigurable hybrid interconnection for static and dynamic scientific applications
Proceedings of the 4th international conference on Computing frontiers
Low Diameter Interconnections for Routing in High-Performance Parallel Systems
IEEE Transactions on Computers
Optics vs. electronics in future high-capacity switches/routers
HPSR'09 Proceedings of the 15th international conference on High Performance Switching and Routing
VLAN-based routing infrastructure for an all-optical circuit switched LAN
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
c-Through: part-time optics in data centers
Proceedings of the ACM SIGCOMM 2010 conference
Helios: a hybrid electrical/optical switch architecture for modular data centers
Proceedings of the ACM SIGCOMM 2010 conference
A compiler-based communication analysis approach for multiprocessor systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
An early performance analysis of POWER7-IH HPC systems
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Proceedings of the 9th conference on Computing Frontiers
OSA: an optical switching architecture for data center networks with unprecedented flexibility
NSDI'12 Proceedings of the 9th USENIX conference on Networked Systems Design and Implementation
A case for random shortcut topologies for HPC interconnects
Proceedings of the 39th Annual International Symposium on Computer Architecture
Performance analysis of an optical circuit switched network for peta-scale systems
Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing
Systolic routing in an optical ring with logarithmic shortcuts
HPCC'07 Proceedings of the Third international conference on High Performance Computing and Communications
Topology configuration in hybrid EPS/OCS interconnects
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
Resource/accuracy tradeoffs in software-defined measurement
Proceedings of the second ACM SIGCOMM workshop on Hot topics in software defined networking
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
A synthetic task model for HPC-grade optical network performance evaluation
IA^3 '13 Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms
Power consumption evaluation of all-optical data center networks
Cluster Computing
A reconfigurable, regular-topology cluster/datacenter network using commodity optical switches
Future Generation Computer Systems
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The interconnect plays a key role in both the cost and performance of large-scale HPC systems. The cost of future high-bandwidth electronic interconnects mushrooms due to expensive optical transceivers needed between electronic switches. We describe a potentially cheaper and more power-efficient approach to building high-performance interconnects.Through empirical analysis of HPC applications, we find that the bulk of inter-processor communication (barring collectives) is bounded in degree and changes very slowly or never. Thus we propose a two-network interconnect: An Optical Circuit Switching (OCS) network handling long-lived bulk data transfers, using optical switches; and a secondary lower-bandwidth Electronic Packet Switching (EPS) network. An OCS could be significantly cheaper, as it uses fewer optical transceivers than an electronic network. Collectives and transient communication packets traverse the electronic network. We present compiler techniques and dynamic run-time policies, using this two-network interconnect. Simulation results show that our approach provides high performance at low cost.