Computer graphics: principles and practice (2nd ed.)
Computer graphics: principles and practice (2nd ed.)
Fast volume rendering using a shear-warp factorization of the viewing transformation
SIGGRAPH '94 Proceedings of the 21st annual conference on Computer graphics and interactive techniques
A compact volume rendering accelerator
VVS '94 Proceedings of the 1994 symposium on Volume visualization
The Heidelberg Ray Tracing Model
IEEE Computer Graphics and Applications
Design of a fast voxel processor for parallel volume visualization
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Towards a scalable architecture for real-time volume rendering
EGGH'95 Proceedings of the Tenth Eurographics conference on Graphics Hardware
Design of a high performance volume visualization system
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
EM-Cube: an architecture for low-cost real-time volume rendering
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
A low-cost memory architecture for PCI-based interactive ray casting
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
GI-cube: an architecture for volumetric global illumination and rendering
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Dependency graph scheduling in a volumetric ray tracing architecture
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Ray Casting Architectures for Volume Visualization
IEEE Transactions on Visualization and Computer Graphics
VoxelCache: a cache-based memory architecture for volume graphics
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
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The computational power required for direct volume rendering like ray-casting or volume ray-tracing can be provided by highspeed rendering architectures. However the increasing processor speed makes a performance bottleneck obvious - the volume memory. This paper describes a volume memory architecture that achieves at least a tenfold speed-up in read-out rate with moderate additional hardware. It has been simulated successfully. A multi-level cache system is used with software prefetching and latency hiding. Pre- and postcaches additionally speed up the read-out rate so that a 5123 data set stored in a single memory module can be rendered at 3.125 Hz.