Novel clock synchronization algorithm of parametric difference for parallel and distributed simulations

  • Authors:

  • Linjun Fan;Yunxiang Ling;Tao Wang;Xiaomin Zhu;Xiaoyong Tang

  • Affiliations:

  • Science and Technology on Information Systems Engineering Laboratory, National University of Defense Technology, Changsha 410073, PR China;Science and Technology on Information Systems Engineering Laboratory, National University of Defense Technology, Changsha 410073, PR China;Faculty of Mathematics and Computer Science, Universitat of Bremen, Bremen 28359, Germany;Science and Technology on Information Systems Engineering Laboratory, National University of Defense Technology, Changsha 410073, PR China;College of Information Science and Technology, Hunan Agricultural University, Changsha 410128, PR China

  • Venue:
  • Computer Networks: The International Journal of Computer and Telecommunications Networking
  • Year:
  • 2013

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Abstract

Clock synchronization is crucial in distributed simulation applications (DSAs). Traditional synchronization methods are mainly based on computers' physical clocks and have network delays. Consequently, the clock jumps easily, and the stability of the algorithm is less than excellent. Furthermore, a new class of DSAs with flexible and dynamically assembled simulation components to optimize the performance of clock clusters is emerging. To remedy the problems, we propose a novel logic parametric difference clock (PDC), which is recursively constructed by an alterable parametric difference frequency (PDF) and its counter. We also develop a simple and efficient synchronization algorithm of parametric difference (SAPD), in which the indeterminate network delay is considered in the PDF, and the PDC counter is used as the synchronous symbol. Compared with existing typical algorithms, the SAPD has the predominant advantages of convergence, stability, and precision for DSAs in local area networks.