Parallel string matching with k mismatches
Theoretical Computer Science
Systematic algorithm mapping for multidimensional systolic arrays
Journal of Parallel and Distributed Computing
Multi-dimensional parallel computing structures for regular iterative algorithms
Integration, the VLSI Journal
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
The ALPHA language and its use for the design of systolic arrays
Journal of VLSI Signal Processing Systems - Special issue: algorithms and parallel VSLI architecture
An introduction to systolic algorithm design
An introduction to systolic algorithm design
Partitioning of processor arrays: a piecewise regular approach
Integration, the VLSI Journal - Special issue on algorithms and architectures
Experimental results on string matching algorithms
Software—Practice & Experience
VASS—a VLSI array system synthesizer
Journal of VLSI Signal Processing Systems
Mesh of linear arrays for template matching
Real-Time Imaging - Special issue on special purpose architectures for real-time imaging
Wormhole run-time reconfiguration
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
The Future of Systems Research
Computer
PARLE '92 Proceedings of the 4th International PARLE Conference on Parallel Architectures and Languages Europe
Loop Parallelization in the Polytope Model
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Cameron: High Level Language Compilation for Reconfigurable Systems
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Formal Derivation of Multilayered Hardware/Software Structures
ICFEM '00 Proceedings of the 3rd IEEE International Conference on Formal Engineering Methods
| Hi-index | 0.00 |
The growing need for high-performance embedded processors on the reconfigurable computing platform increases the pressure for developing design methods and tools. One important issue in mapping algorithms into hardware is the configuring of algorithms to fit the particular hardware structure, the available area and configuration, together with time parameters. This paper presents an overview of a new synthesis method—the Iso-plane method—on the polytope model of algorithm to increase the parallelism and facilitate the configurability in regular array design via algebraic transformations as associativity and commutativity. The paper presents a variety of new regular and scalable array solutions with improved performance and better layout including motherboards with daughter boards.