Dynamic test signal design for analog ICs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
CONCERT: a concurrent transient fault simulator for nonlinear analog circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis
Proceedings of the IEEE International Test Conference
Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
An Integrated Approach for Analog Ciruit Testing with a Minmum Number of Detected Parameters
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test Vector Generation for Linear Analog Devices
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A novel test generation approach for parametric faults in linear analog circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test generation based diagnosis of device parameters for analog circuits
Proceedings of the conference on Design, automation and test in Europe
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In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-under-test, the proposed test generator computes the optimal transient test stimuli in order to detect and isolate a given set of faults. It also computes the optimal set of test nodes to probe at, and the time instants to make measurements. The test generation program accommodates the effects introduced by component tolerances and measurement inaccuracy, and can be tailored to fit the signal generation capabilities of a hardware tester. Experimental results show that the proposed technique can be applied to generate transient tests for both linear and non-linear analog circuits of moderate complexity in reasonably less CPU time. This will significantly impact the test development costs for an analog circuit and will decrease the time-to-market of a product. Finally, the short duration and the easy-to-apply feature of the test stimuli will lead to significant reduction in production test costs.