Fault Diagnosis for Linear Analog Circuits

Authors:
Jun Weir Lin;Chung Len Lee;Chau Chin Su;Jwu-E. Chen
Affiliations:
Department of Electronics Engineering, National Chiao Tung University, Hsin Chu, Taiwan, R.O.C. jwlin@dragon.ee.nctu.edu.tw;Department of Electronics Engineering, National Chiao Tung University, Hsin Chu, Taiwan, R.O.C. cllee@cc.nctu.edu.tw;Department of Electrical Engineering, National Central University, Chung-Li, Taiwan, R.O.C;Department of Electrical Engineering, Chung Hwa University, Hsin Chu, Taiwan, R.O.C
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2001

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Abstract

This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs “diagnosing evaluators,” which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as active faults in OP's.