A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

Authors:
Konstantinos Masselos;Francky Catthoor;Costas E. Goutis;Hugo Deman
Affiliations:
Department of Electrical and Computer Engineering, University of Patras, Rio 26500, Greece;Inter-University Microelecronics-Centre (IMEC), B-3001 Leuven, Belgium and Katholieke Universiteit Leuven, Leuven 3001, Belgium;Department of Electrical and Computer Engineering, University of Patras, Rio 26500, Greece;Inter-University Microelecronics-Centre (IMEC), B-3001 Leuven, Belgium and Katholieke Universiteit Leuven, Leuven 3001, Belgium
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2002

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Abstract

A systematic methodology for the reduction of the power consumption and the execution time in realizations of multimedia applications on programmable processors is proposed. The methodology is mainly based on the application of data transfer and storage optimizing code transformations to a high-level description of the target algorithm. Application of the code transformations according to the proposed order moves the main part of the memory accesses from the large background memories (lying possibly off-chip) to smaller ones (on-chip) or even to foreground storage. Data cache performance is improved as well. In this way the power consumption in the data memory hierarchy of the target processor and in the related interconnect, which forms a significant part of the total power budget of the system, is heavily reduced. Execution time and the power consumption due to instruction storage and transfers are reduced as well after the application of the proposed methodology. Experimental results from real-life applications prove the effectiveness of the proposed methodology.