Efficient context-sensitive pointer analysis for C programs
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Points-to analysis in almost linear time
POPL '96 Proceedings of the 23rd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Leakage-proof program partitioning
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Tamper Resistant Software: An Implementation
Proceedings of the First International Workshop on Information Hiding
Probing Attacks on Tamper-Resistant Devices
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Investigations of power analysis attacks on smartcards
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Tamper resistance: a cautionary note
WOEC'96 Proceedings of the 2nd conference on Proceedings of the Second USENIX Workshop on Electronic Commerce - Volume 2
On the importance of checking cryptographic protocols for faults
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
Profile Guided Management of Code Partitions for Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
HIDE: an infrastructure for efficiently protecting information leakage on the address bus
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
A fast, memory-efficient register allocation framework for embedded systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Planning for code buffer management in distributed virtual execution environments
Proceedings of the 1st ACM/USENIX international conference on Virtual execution environments
Automatically partitioning packet processing applications for pipelined architectures
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
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Due to limited available memory (of the order of Kilobytes) on embedded devices (such as smart cards), we undertake an approach of partitioning the whole program when it does not fit in the memory. The program partitions are downloaded from the server on demand into the embedded device just before execution. We devise a method of partitioning the code and data of the program such that no information regarding the control flow behavior of the program is leaked out. This property is called tamper resistance and it is very important for secure embedded devices such as smart cards which could hold sensitive information and/or carry out critical computation such as financial transactions. A preliminary solution to this problem was proposed in our earlier work [1]. This work proposes a new and more comprehensive solution to the problem. First, we propose a new policy which is based on keeping nothing in terms of partitions on the smart card. This policy is unlike the one in previous work which mandated keeping partitions in memory to which control flow was guaranteed to return. Based on this new policy, a new partitioning algorithm is proposed for minimal safe partitions which reduces their memory requirements over previous work. The drawback of this new policy is however lower execution speed due to frequent communication encountered. In order to not significantly degrade performance, we propose caching frequently executed functions on the smart card without violation of tamper resistance. A framework is designed to determine the set of functions to be cached in conjunction with specific minimal safe partitions. Further reduction in memory requirements is achieved due to the data partitioning.The decrease in memory footprint over the previous method is 27% for code memory and 32.4% for data memory on average. The speed-up over the old method is quite significant when applied to whole programs in large benchmarks (500 times on average). The conclusion is that previous method [1] is not suitable as a whole program partitioning strategy whereas the new proposed method is a viable solution.