Multifrequency Analysis of Faults in Analog Circuits
IEEE Design & Test
iDD Pulse Response Testing of Analog and Digital CMOS Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
ICCQ: A Test Method for Analogue VLSI Base On Current Monitoring
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
A Signature Test Framework for Rapid Production Testing of RF Circuits
Proceedings of the conference on Design, automation and test in Europe
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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AC sensitivities guide most Analogue Automatic Test Pattern Generator (AATPG) while determining the optimal frequencies of a sinusoidal test stimulus. The optimal frequencies thus determined, normally lie in the close vicinity of the operating frequency of the circuit. Although these frequencies are justifiable by the principles of the circuit, these test frequencies do not bring any added value to the ultimate goal of cheap alternatives (low frequency test signal and cheaper measurement equipment) for the analogue and RF tests. In this paper, we propose to re-configure the circuit blocks, in such a way that the operating frequencies of the respective sub-block are shifted to lower testable frequencies. We have validated our proposal on a sub-block of a satellite receiver circuit that resulted in lowering the test frequencies of the corresponding sub-blocks from 12 GHz to 4MHz, while attaining the same level of defect coverage.