Talisman: commodity realtime 3D graphics for the PC
SIGGRAPH '96 Proceedings of the 23rd annual conference on Computer graphics and interactive techniques
Rendering from compressed textures
SIGGRAPH '96 Proceedings of the 23rd annual conference on Computer graphics and interactive techniques
High quality rendering using the Talisman architecture
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Accommodating memory latency in a low-cost rasterizer
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Rendering with coherent layers
Proceedings of the 24th annual conference on Computer graphics and interactive techniques
The design and analysis of a cache architecture for texture mapping
Proceedings of the 24th annual international symposium on Computer architecture
Prefetching in a texture cache architecture
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Meshed atlases for real-time procedural solid texturing
ACM Transactions on Graphics (TOG)
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Low latency photon mapping using block hashing
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
Random Access Decompression using Binary Arithmetic Coding
DCC '99 Proceedings of the Conference on Data Compression
Compressed caching and modern virtual memory simulation
Compressed caching and modern virtual memory simulation
iPACKMAN: high-quality, low-complexity texture compression for mobile phones
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
ETC2: texture compression using invalid combinations
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
Floating-point buffer compression in a unified codec architecture
Proceedings of the 23rd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
Technical Section: ftc-Floating precision texture compression
Computers and Graphics
Lossless compression of already compressed textures
Proceedings of the ACM SIGGRAPH Symposium on High Performance Graphics
Variable bit rate GPU texture decompression
EGSR'11 Proceedings of the Twenty-second Eurographics conference on Rendering
Compressed random-access trees for spatially coherent data
EGSR'07 Proceedings of the 18th Eurographics conference on Rendering Techniques
Adaptive Compression of Texture Pyramids
Computer Graphics Forum
Topographic map visualization from adaptively compressed textures
EuroVis'10 Proceedings of the 12th Eurographics / IEEE - VGTC conference on Visualization
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A number of texture compression algorithms have been proposed to reduce texture storage size and bandwidth requirements. To deal with the requirement for random access, these algorithms usually divide the texture into tiles and apply a fixed rate compression scheme to each tile. Fixed rate schemes are by nature lossy, and cannot adapt to local changes in image complexity. Multiresolution schemes, a form of variable-rate coding, can adapt to varying image complexity but suffer from fragmentation and can only compress a limited class of images. On the other hand, several lossless image compression standards have been established. Lossless compression requires variable-rate coding, and more efficient lossy algorithms also use variable-rate coding. Unfortunately, these standards cannot be used directly as texture compression schemes since they do not allow random access. We present a block-oriented lossless texture compression algorithm based on a simple variable-bitrate differencing scheme. A B-tree index enables both random access and efficient 0(1) memory allocation without external fragmentation. Textures in our test suite compressed to between 6% and 95% of their original sizes. We propose a cache architecture designed to support our compression scheme. Cycle-accurate simulation shows that this cache architecture consistently reduces the external bandwidth requirements as well as the storage size without significantly affecting latency.