Energy-efficient variable-flow liquid cooling in 3D stacked architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
Microelectronics Journal
System-level power and timing variability characterization to compute thermal guarantees
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Convex-based thermal management for 3D MPSoCs using DVFS and variable-flow liquid cooling
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Toward five-dimensional scaling: how density improves efficiency in future computers
IBM Journal of Research and Development
3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling
Proceedings of the International Conference on Computer-Aided Design
Fuzzy control for enforcing energy efficiency in high-performance 3D systems
Proceedings of the International Conference on Computer-Aided Design
Accelerating thermal simulations of 3D ICs with liquid cooling using neural networks
Proceedings of the great lakes symposium on VLSI
A liquid cooling solution for temperature redistribution in 3D IC architectures
Microelectronics Journal
Integration, the VLSI Journal
Roadmap towards ultimately-efficient zeta-scale datacenters
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
The heat-removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters ≤200 μm. An experimental investigation with uniform and double-side heat flux at Reynolds numbers ≤1,000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. The following structures were tested: parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 μm and fluid structure heights of 100–200 μm. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin in-line structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks having a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from 200 W/cm2 at 1 cm2 and 50 μm interconnect pitch to 2 at 4 cm2. From experimental data, friction factor and Nusselt number correlations were derived for pin fin in-line and staggered structures.