Relaxation techniques for the simulation of VLSI circuits
Relaxation techniques for the simulation of VLSI circuits
A multilevel algorithm for partitioning graphs
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
An Approximate Minimum Degree Ordering Algorithm
SIAM Journal on Matrix Analysis and Applications
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hypergraph-Partitioning-Based Decomposition for Parallel Sparse-Matrix Vector Multiplication
IEEE Transactions on Parallel and Distributed Systems
On Identifying Strongly Connected Components in Parallel
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
SuperLU_DIST: A scalable distributed-memory sparse direct solver for unsymmetric linear systems
ACM Transactions on Mathematical Software (TOMS)
Iterative Methods for Sparse Linear Systems
Iterative Methods for Sparse Linear Systems
Solving unsymmetric sparse systems of linear equations with PARDISO
Future Generation Computer Systems - Special issue: Selected numerical algorithms
An overview of the Trilinos project
ACM Transactions on Mathematical Software (TOMS) - Special issue on the Advanced CompuTational Software (ACTS) Collection
Finding strongly connected components in distributed graphs
Journal of Parallel and Distributed Computing
Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2)
Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2)
Parallel domain decomposition for simulation of large-scale power grids
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Partitioning Sparse Matrices for Parallel Preconditioned Iterative Methods
SIAM Journal on Scientific Computing
Parallel transistor level circuit simulation using domain decomposition methods
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast circuit simulation on graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Parallel iterative solvers for sparse linear systems in circuit simulation
Future Generation Computer Systems
A parallel approximation algorithm for the weighted maximum matching problem
PPAM'07 Proceedings of the 7th international conference on Parallel processing and applied mathematics
Parallel hypergraph partitioning for scientific computing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power Grid Analysis and Optimization Using Algebraic Multigrid
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel circuit simulation with adaptively controlled projective integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 49th Annual Design Automation Conference
Enabling next-generation parallel circuit simulation with trilinos
Euro-Par'11 Proceedings of the 2011 international conference on Parallel Processing
Proceedings of the International Conference on Computer-Aided Design
A new time-stepping method for circuit simulation
Proceedings of the 50th Annual Design Automation Conference
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We describe a parallel computing approach for large-scale SPICE-accurate circuit simulation, which is based on a new strategy for the parallel preconditioned iterative solution of circuit matrices. This strategy consists of several steps, including singleton removal, block triangular form (BTF) reordering, hypergraph partitioning, and a block Jacobi pre-conditioner. Our parallel implementation makes use of a mixed load balance, employing a different parallel partition for the matrix load and solve. Based on message-passing, our circuit simulation code was originally designed for large parallel computers, but for the purposes of this paper we demonstrate that it also gives good parallel speedup in modern multi-core environments. We show that our new parallel solver outperforms a serial direct solver, a parallel direct solver and an alternative iterative solver on a set of circuit test problems.