An Analysis of Bitstate Hashing
Formal Methods in System Design
Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Model Checking without BDDs
TACAS '99 Proceedings of the 5th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Using Magnatic Disk Instead of Main Memory in the Murphi Verifier
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
ESA '01 Proceedings of the 9th Annual European Symposium on Algorithms
GPUTeraSort: high performance graphics co-processor sorting for large database management
Proceedings of the 2006 ACM SIGMOD international conference on Management of data
A general lock-free algorithm using compare-and-swap
Information and Computation
The Design of a Multicore Extension of the SPIN Model Checker
IEEE Transactions on Software Engineering
Disk Based Software Verification via Bounded Model Checking
APSEC '07 Proceedings of the 14th Asia-Pacific Software Engineering Conference
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Semi-external LTL Model Checking
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Dynamic Delayed Duplicate Detection for External Memory Model Checking
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Layered Duplicate Detection in External-Memory Model Checking
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Efficient Probabilistic Model Checking on General Purpose Graphics Processors
Proceedings of the 16th International SPIN Workshop on Model Checking Software
Efficient large-scale model checking
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Cache-, hash-, and space-efficient bloom filters
Journal of Experimental Algorithmics (JEA)
CUDA Accelerated LTL Model Checking
ICPADS '09 Proceedings of the 2009 15th International Conference on Parallel and Distributed Systems
Minimal counterexample generation for SPIN
Proceedings of the 14th international SPIN conference on Model checking software
BEEM: benchmarks for explicit model checkers
Proceedings of the 14th international SPIN conference on Model checking software
Accelerating large graph algorithms on the GPU using CUDA
HiPC'07 Proceedings of the 14th international conference on High performance computing
Revisiting resistance speeds up I/O-efficient LTL model checking
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Large-Scale directed model checking LTL
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
Designing fast LTL model checking algorithms for many-core GPUs
Journal of Parallel and Distributed Computing
Self-adaptive containers: building resource-efficient applications with low programmer overhead
Proceedings of the 8th International Symposium on Software Engineering for Adaptive and Self-Managing Systems
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We accelerate state space exploration for explicit-state model checking by executing complex operations on the graphics processing unit (GPU). In contrast to existing approaches enhancing model checking through performing parallel matrix operations on the GPU, we parallelize the breadth-first layered construction of the state space graph. For efficient processing, the input model is translated to the reverse Polish notation, resulting in a representation as an integer vector. The proposed GPU exploration algorithm then divides into two parallel stages. In the first stage, each state is replaced with a Boolean vector to denote which transitions are enabled. In the second stage, pairs consisting of replicated states and enabled transition IDs are copied to the GPU then all transitions are applied in parallel to produce the successors. Bitstate hashing is used as a Bloom filter to remove duplicates from the set of successors in RAM. The experiments show speed-ups of about one order of magnitude. Compared to state-of-the-art in multi-core model checking software, still advances remain visible.