SIGGRAPH '86 Proceedings of the 13th annual conference on Computer graphics and interactive techniques
Rendering complex scenes with memory-coherent ray tracing
Proceedings of the 24th annual conference on Computer graphics and interactive techniques
Fast, minimum storage ray-triangle intersection
Journal of Graphics Tools
Geometry caching for ray-tracing displacement maps
Proceedings of the eurographics workshop on Rendering techniques '96
GI-cube: an architecture for volumetric global illumination and rendering
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
An improved illumination model for shaded display
Communications of the ACM
Efficiency issues for ray tracing
Journal of Graphics Tools
A low power architecture for embedded perception
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Multi-level ray tracing algorithm
ACM SIGGRAPH 2005 Papers
Reordering for cache conscious photon mapping
GI '05 Proceedings of Graphics Interface 2005
Packet-based whitted and distribution ray tracing
GI '07 Proceedings of Graphics Interface 2007
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Larrabee: a many-core x86 architecture for visual computing
ACM SIGGRAPH 2008 papers
StreamRay: a stream filtering architecture for coherent ray tracing
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Toward a multicore architecture for real-time ray-tracing
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
RT '07 Proceedings of the 2007 IEEE Symposium on Interactive Ray Tracing
Realtime Ray Tracing on GPU with BVH-based Packet Traversal
RT '07 Proceedings of the 2007 IEEE Symposium on Interactive Ray Tracing
Rigel: an architecture and scalable programming interface for a 1000-core accelerator
Proceedings of the 36th annual international symposium on Computer architecture
Faster incoherent rays: Multi-BVH ray stream tracing
Proceedings of the Conference on High Performance Graphics 2009
TRaX: a multicore hardware architecture for real-time ray tracing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cache-oblivious ray reordering
ACM Transactions on Graphics (TOG)
Restart trail for stackless BVH traversal
Proceedings of the Conference on High Performance Graphics
Architecture considerations for tracing incoherent rays
Proceedings of the Conference on High Performance Graphics
Real-time ray tracer for visualizing massive models on a cluster
EG PGV'11 Proceedings of the 11th Eurographics conference on Parallel Graphics and Visualization
Efficient stack-less BVH traversal for ray tracing
Proceedings of the 27th Spring Conference on Computer Graphics
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We propose two hardware mechanisms to decrease energy consumption on massively parallel graphics processors for ray tracing while keeping performance high. First, we use a streaming data model and configure part of the L2 cache into a ray stream memory to enable efficient data processing through ray reordering. This increases the L1 hit rate and reduces off-chip memory accesses substantially. Second, we employ reconfigurable special-purpose pipelines than are constructed dynamically under program control. These pipelines use shared execution units (XUs) that can be configured to support the common compute kernels that are the foundation of the ray tracing algorithm, such as acceleration structure traversal and triangle intersection. This reduces the overhead incurred by memory and register accesses. These two synergistic features yield a ray tracing architecture that significantly reduces both power consumption and off-chip memory traffic when compared to a more traditional cache only approach.