A Configurable Pixel Cache for Fast Image Generation
IEEE Computer Graphics and Applications
The Reyes image rendering architecture
SIGGRAPH '87 Proceedings of the 14th annual conference on Computer graphics and interactive techniques
Hierarchical Z-buffer visibility
SIGGRAPH '93 Proceedings of the 20th annual conference on Computer graphics and interactive techniques
Triangle scan conversion using 2D homogeneous coordinates
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Neon: a single-chip 3D workstation graphics accelerator
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Pomegranate: a fully scalable graphics architecture
Proceedings of the 27th annual conference on Computer graphics and interactive techniques
An improved illumination model for shaded display
Communications of the ACM
Efficient conditional operations for data-parallel architectures
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
A parallel algorithm for polygon rasterization
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A user-programmable vertex engine
Proceedings of the 28th annual conference on Computer graphics and interactive techniques
Proceedings of the 28th annual conference on Computer graphics and interactive techniques
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
The SAGE graphics architecture
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
Ray tracing on programmable graphics hardware
Proceedings of the 29th annual conference on Computer graphics and interactive techniques
Dynamic Acceleration Structures for Interactive Ray Tracing
Proceedings of the Eurographics Workshop on Rendering Techniques 2000
Photon mapping on programmable graphics hardware
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
ACM SIGGRAPH 2003 Papers
A subdivision algorithm for computer display of curved surfaces.
A subdivision algorithm for computer display of curved surfaces.
Spinach: a liberty-based simulator for programmable network interface architectures
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
An approximate global illumination system for computer generated films
ACM SIGGRAPH 2004 Papers
Memory Controller Optimizations for Web Servers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Scatter-Add in Data Parallel Architectures
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
The Liberty Simulation Environment, version 1.0
ACM SIGMETRICS Performance Evaluation Review - Special issue on tools for computer architecture research
Glift: Generic, efficient, random-access GPU data structures
ACM Transactions on Graphics (TOG)
EGSR'04 Proceedings of the Fifteenth Eurographics conference on Rendering Techniques
Glift: Generic, efficient, random-access GPU data structures
ACM Transactions on Graphics (TOG)
Proceedings of the 4th international conference on Computer graphics and interactive techniques in Australasia and Southeast Asia
Real-time rendering systems in 2010
SIGGRAPH '05 ACM SIGGRAPH 2005 Courses
Proceedings of the 2007 symposium on Interactive 3D graphics and games
GI '07 Proceedings of Graphics Interface 2007
Practical logarithmic rasterization for low-error shadow maps
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
Resolution-matched shadow maps
ACM Transactions on Graphics (TOG)
Larrabee: a many-core x86 architecture for visual computing
ACM SIGGRAPH 2008 papers
Logarithmic perspective shadow maps
ACM Transactions on Graphics (TOG)
Soft irregular shadow mapping: fast, high-quality, and robust soft shadows
Proceedings of the 2009 symposium on Interactive 3D graphics and games
Proceedings of the Conference on High Performance Graphics 2009
ACM SIGGRAPH ASIA 2009 Courses
Sample distribution shadow maps
I3D '11 Symposium on Interactive 3D Graphics and Games
Proceedings of the 2011 SIGGRAPH Asia Conference
Rectilinear texture warping for fast adaptive shadow mapping
I3D '12 Proceedings of the ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games
3D rasterization: a bridge between rasterization and ray casting
Proceedings of Graphics Interface 2012
International Journal of High Performance Computing Applications
ACM SIGGRAPH 2012 Courses
Camera space volumetric shadows
Proceedings of the Digital Production Symposium
Sample based visibility for soft shadows using alias-free shadow maps
EGSR'08 Proceedings of the Nineteenth Eurographics conference on Rendering
Real-time concurrent linked list construction on the GPU
EGSR'10 Proceedings of the 21st Eurographics conference on Rendering
High resolution sparse voxel DAGs
ACM Transactions on Graphics (TOG) - SIGGRAPH 2013 Conference Proceedings
Proceedings of the 19th ACM Symposium on Virtual Reality Software and Technology
ACM SIGGRAPH 2013 Courses
Proceedings of the 18th meeting of the ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games
Per-triangle shadow volumes using a view-sample cluster hierarchy
Proceedings of the 18th meeting of the ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games
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The classical Z-buffer visibility algorithm samples a scene at regularly spaced points on an image plane. Previously, we introduced an extension of this algorithm called the irregular Z-buffer that permits sampling of the scene from arbitrary points on the image plane. These sample points are stored in a two-dimensional spatial data structure. Here we present a set of architectural enhancements to the classical Z-buffer acceleration hardware which supports efficient execution of the irregular Z-buffer. These enhancements enable efficient parallel construction and query of certain irregular data structures, including the grid of linked lists used by our algorithm. The enhancements include flexible atomic read-modify-write units located near the memory controller, an internal routing network between these units and the fragment processors, and a MIMD fragment processor design. We simulate the performance of this new architecture and demonstrate that it can be used to render high-quality shadows in geometrically complex scenes at interactive frame rates. We also discuss other uses of the irregular Z-buffer algorithm and the implications of our architectural changes in the design of chip-multiprocessors.