Fairness
Modalities for model checking: branching time logic strikes back
Science of Computer Programming
The &mgr;-calculus as an assertion-language for fairness arguments
Information and Computation
Completing the temporal picture
Selected papers of the 16th international colloquium on Automata, languages, and programming
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Temporal verification of reactive systems: safety
Temporal verification of reactive systems: safety
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Verification by augmented finitary abstraction
Information and Computation
On the temporal analysis of fairness
POPL '80 Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Another Look at LTL Model Checking
Formal Methods in System Design
Faster Algorithms for the Nonemptiness of Streett Automata and for Communication Protocol Pruning
SWAT '96 Proceedings of the 5th Scandinavian Workshop on Algorithm Theory
Impartiality, Justice and Fairness: The Ethics of Concurrent Termination
Proceedings of the 8th Colloquium on Automata, Languages and Programming
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
Efficient omega-Regular Language Containment
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
A Platform for Combining Deductive with Algorithmic Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Proceedings of the Conference on Logic of Programs
Algorithmic Verification of Linear Temporal Logic Specifications
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
A compositional approach to CTL* verification
Theoretical Computer Science - Formal methods for components and objects
Local Proofs for Linear-Time Properties of Concurrent Programs
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Specifying and Verifying Event-Based Fairness Enhanced Systems
ICFEM '08 Proceedings of the 10th International Conference on Formal Methods and Software Engineering
PAT: Towards Flexible Verification under Fairness
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Fair Model Checking with Process Counter Abstraction
FM '09 Proceedings of the 2nd World Congress on Formal Methods
Scalable Multi-core Model Checking Fairness Enhanced Systems
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
State/event-based LTL model checking under parametric generalized fairness
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Model checking LTLR formulas under localized fairness
WRLA'12 Proceedings of the 9th international conference on Rewriting Logic and Its Applications
An algorithm on fairness verification of mobile sink routing in wireless sensor network
Personal and Ubiquitous Computing
Model checking with fairness assumptions using PAT
Frontiers of Computer Science: Selected Publications from Chinese Universities
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In this paper we present a coherent framework for symbolic model checking of linear-time temporal logic (ltl) properties over finite state reactive systems, taking full fairness constraints into consideration. We use the computational model of a fair discrete system (fds) which takes into account both justice (weak fairness) and compassion (strong fairness). The approach presented here reduces the model-checking problem into the question of whether a given fds is feasible (i.e. has at least one computation).The contribution of the paper is twofold: On the methodological level, it presents a direct self-contained exposition of full ltl symbolic model checking without resorting to reductions to either 驴-calculus or ctl. On the technical level, it extends previous methods by dealing with compassion at the algorithmic level instead of either adding it to the specification, or transforming compassion to justice.Finally, we extend ctl驴 with past operators, and show that the basic symbolic feasibility algorithm presented here, can be used to model check an arbitrary ctl驴 formula over an fds with full fairness constraints.