System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Random Data: Analysis and Measurement Procedures
Random Data: Analysis and Measurement Procedures
Mixed-Signal Circuit Classification in a Pseudo-Random Testing Scheme
Journal of Electronic Testing: Theory and Applications
Analog and Mixed-Signal Benchmark Circuits-First Release
Proceedings of the IEEE International Test Conference
Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Ultra Low Cost Analog BIST Using Spectral Analysis
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Specification Test Compaction for Analog Circuits and MEMS
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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In this work a BIST method for linear analog circuits with very low cost and the smallest possible analog overhead area is presented. The method is suitable to be implemented in the SoC environment, as it allows the reuse of resources already available in the system, and it is essentialy digital. Theoretical background is provided, and experimental results demonstrate the advantages and limits of the proposed approach.